1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for fabricating a semiconductor device.
2. Background of the Related Art
A related art dual gate in a semiconductor device will now be described. FIGS. 1Axcx9c1E illustrate sections showing the steps of a related art method for fabricating a dual gate.
As shown in FIG. 1A, the related art method for fabricating a dual gate starts with forming device isolating layers 2 in device isolating regions of a semiconductor substrate 1 by LOCOS or STI. N type and P type impurity ions are implanted in active regions defined by the device isolating regions 2 to form P type well region 3 and N type well region 4. Then, a gate oxide film 5, and an undoped polysilicon layer 6 as a gate forming material layer are formed on an entire surface inclusive of the P type well region 3 and the N type well region 4. A photoresist film is coated on an entire surface, and selectively patterned, to form a first photoresist film pattern layer 7. The first photoresist film pattern layer 7 is used as a mask in implanting xe2x80x98nxe2x80x99 type impurity ions in an exposed surface of the undoped polysilicon layer 6. The xe2x80x98nxe2x80x99 type impurity ion implantation forms an xe2x80x98nxe2x80x99 type impurity implanted layer 6a on the P type well region 3.
As shown in FIG. 1B, the first photoresist film pattern layer 7 is removed. A photoresist film is coated again, and selectively removed to leave the photoresist film only on the P type well region 3, which forms a second photoresist pattern layer 8. The second photoresist pattern layer 8 is used as a mask in implanting xe2x80x98pxe2x80x99 type impurity ions in an exposed surface of the undoped polysilicon layer 6. The xe2x80x98pxe2x80x99 type impurity ion implantation forms a xe2x80x98pxe2x80x99 type impurity implanted layer 6b on the N type well region 4.
As shown in FIG. 1C, a barrier layer 10 of a tungsten silicide or tungsten, and a hard mask layer 11 for gate patterning are formed on the xe2x80x98nxe2x80x99 type impurity implanted layer 6a and the xe2x80x98pxe2x80x99 type impurity implanted layer 6b. The hard mask layer 11 for gate patterning is formed of an oxide or a nitride. Then, a photoresist film is coated on the hard mask layer 11 and selectively patterned to form a third photoresist film pattern layer 9
As shown in FIG. 1D, the third photoresist film pattern layer 9 is used as mask in selectively patterning exposed portions of the hard mask layer 11 for gate patterning, which is used as a hard mask in selectively etching the barrier layer 10, and the polysilicon layers 6a and 6b to form gates 12a and 12b. As shown in FIG. 1E, an oxide or nitride film is deposited on an entire surface inclusive of the gates 12a and 12b, and subjected to anisotropic etching to form sidewalls 13 at sides of the gates. Though not shown on the drawing, photoresist film mask patterns are alternatively formed on the P type well 3 and the N type well 4 to implant n type impurities in the P type well region 3 by using the gate 12a as a mask to form source/drain regions 14a, and to implant p type impurities in the n type well region 4 by using the gate 12b as a mask to form source/drain regions 14b. Thus, by forming an n-polygate and a p-polygate on one wafer in the same process, fabrication of a logic circuit is made simple.
As described above, the related art method for fabricating a dual gate has various disadvantages. Since the dual gate is formed by implanting impurity ions using a single polysilicon layer, the gate short channel effect caused by employment of a buried PMOS, if a PMOS is required, for optimization of device performances impedes formation of a device having a gate length below 0.25 xcexcm. Further, the formation of two sheets of masks required after deposition of the polysilicon layer and in the formation of the source/drain in fabrication of the dual gate (i.e., for providing an n-poly in an NMOS, and a p-poly in a PMOS) leads to additional fabrication steps that increase production costs. The implantation of ions in the polysilicon layer can damage the gate oxide film if the polysilicon layer is thin (below 500 xc3x85), which impedes a regular fabrication because too low an energy should be used in implanting ions in formation of p+ poly. Since it is impossible to drop a sheet resistivity below 10 xcexa9/m even if the tungsten silicide is deposited to a thickness greater than than 1000 xc3x85 as the tungsten silicide has at best a resistivity in a range of 100 xcexcxcexa9m, the tungsten silicide is not suitable for use as a barrier layer. If a tungsten layer, not the tungsten silicide layer, is used to reduce the resistance, an additional diffusion barrier of TiN or WN is required to prevent a reaction with silicon. Also, a re-oxidation is required for restoring the damage to the gate oxide film from the etching since the tungsten is vulnerable to reaction with oxygen, which causes selective oxidation. However, the selective oxidation has difficulty in process control that deteriorates reproducibility. See S. Iwata et al., IEEE Trans. Elec. Dev. ED-31, 1174 (1984). The re-oxidation causes a problem of oxidizing the polycide. See M. Tanielian et al., IEEE Tran. Elec. Dev. Lett. EDL-6, 221 (1985), and K. A. Jenkins et al., Tech. Dig Int. Elec. Dev. Meet., 891(1993).
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that substantially obviates one or more problems caused by limitations and disadvantages of the related art.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device having a dual gate of cobalt polycide.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that has an excellent thermal stability and a low resistance.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that can be patterned using a time and cost efficient fabrication process.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that has a reduced gate length below 0.25 xcexcm.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that implants source/drain regions concurrently with gate ions.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that diffuses ions into a silicide layer to reduce a thickness of a polysilicon layer.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that can eliminate a low energy ion implanting equipment from a fabrication process.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that has a low resistivity without a diffusion prevention layer in the gate electrode.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that reduces oxidation damage to a polycide layer.
To achieve at least these objects and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a method for fabricating a polycide dual gate in a semiconductor device includes (1) forming polysilicon pattern layers on a first and a second regions of a semiconductor substrate, (2) forming a blocking layer level with exposed top surfaces of the polysiliconpattern layers, (3) forming and annealing a cobalt layer on an entire surface to form a gate electrode having a stack of the polysilicon pattern layer and a cobalt silicide layer, and (4) implanting ions of opposite conductivities in the first and second regions respectively and annealing to form source/drain regions in surfaces of the substrate on both sides of the gate electrode, and to implant gate ions in the polysilicon pattern layer.
To further achieve the above objects and advantages in a whole or in part, there is provided a method for fabricating a polycide dual gate in a semiconductor device that includes forming polysilicon pattern layers over a first and a second regions of a semiconductor substrate, forming a blocking layer to expose top surfaces of the polysilicon pattern layers, annealing a refractory metal into the polysilicon patterns to form a gate electrode having a refractory metal silicide layer and forming source/drain regions in surfaces of the substrate on both sides of the gate electrodes.
To further achieve the above objects and advantages in a whole or in part, there is provided a method for fabricating a polycide dual gate in a semiconductor device that includes forming a first conductivity type well region and a second conductivity type well region in surfaces of a semiconductor substrate, forming a gate oxide film and an undoped polysilicon layer on the well regions of the substrate that are selectively etched to form polypattern layers, implanting first conductivity type impurity ions in the polypattern layers over the second conductivity type well region and an exposed surface of the second conductivity type well region, implanting second conductivity type impurity ions in the polypattern layers over the first conductivity type well region and an exposed surface of the first conductivity type well region, annealing to form first conductivity type sources/drains in the second conductivity type well region and second conductivity type sources/drains in the first conductivity type well region, forming sidewalls at sides of the polypattern layers, forming a blocking layer to expose top surfaces of the polypattern layers and to mask a surface of the substrate and depositing a cobalt layer on an entire surface and annealing to form gate electrodes each having a polycide structure with a stack of the polypattern layer below a silicide layer.
To further achieve the above objects and advantages in a whole or in part, there is provided a method for fabricating a polycide dual gate in a semiconductor device that includes forming a first conductivity type well region and an second conductivity type well region in surfaces of a semiconductor substrate, forming a gate oxide film and an undoped polysilicon layer that are selectively etched to form polypattern layers on the well regions, forming a blocking layer to expose top surfaces of the polypattern layers and mask the well regions, depositing a cobalt layer on the polypattern layers and the blocking layer, annealing to form gate electrodes of a polycide structure each with a stack of the polypattern layer and a silicide layer, forming sidewalls at sides of the gate electrodes, implanting second conductivity type impurity ions and first conductivity type impurity ions in the first conductivity type well region and the second conductivity type well region, respectively, and diffusing to form source/drain regions.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.